Clock speed change

JrWin · **註冊時間:** 三月 8th, 2010, 9:42 am **文章:** 1

Hi,

I am working on a CPLD project. The program was originally sending 8-bits data in parallel. Now I have to change it to send the data in serial.

So the clock speed was set to 8 times faster. But the problem is that the
data still have to be read from the buffer in parallel before sending.

The original coding for the parallel data output is as following:

代碼:

always @ (iPSClk)        // clock for parallel data output
begin
    if(iPSClk)
        oRead = 0;          // triggers read at the falling edge;
    else
        oRead = 1;
end

Then it was modified for the serial output:

代碼:

always @(rBitCnt)
begin
    if((rBitCnt == 4) || (rBitCnt == 5) || (rBitCnt == 6) || (rBitCnt == 7))
         oRead = 0;
    else
         oRead = 1;
end

always @(negedge iPSClk2)    // new clock for serial output
begin
    if(rBitCnt < 7)
         rBitCnt = rBitCnt + 1;
    else
         rBitCnt = 0;
end

The oRead signals measured by the analyzer are in the same timing, however, the program is not working.

So it will be great help, if anyone knows better ways to remain the oRead timing with new faster clock.

Thank you,
JR

FPGA fancier

Clock speed change

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